1. Field of the Invention
The present invention relates to a data transmitting device for formatting data into packets and transmitting the data packets. In particular, the present invention relates to a packet output device for reducing the load of a packet generator of the data transmitting device by adding transmission time data to the data packets.
2. Description of the Related Art
In digital data communication, data transmission is generally performed using a packet as a unit of data. An IEEE 1394 interface is one of such interfaces performing data communication using packets. The IEEE 1394 is a serial interface having a high data transmission rate for the next generation multimedia standardized by the IEEE (for example, refer to High Performance Serial Bus P1394/Draft 8.0 v2). At present, an IEEE 1394 interface has been developed for use in digital audio visual (AV) equipment.
The IEEE 1394 can transmit two types of packets, i.e., isochronous packets for transmitting data which requires real-time transfer and asynchronous packets for transmitting data which does not require the real-time transfer. For example, digital audio visual (AV) data is communicated in the isochronous transfer mode using common isochronous packets.
In order to determine a buffer size for transmitting and receiving data requiring real-time transfer, it is necessary to determine a packet transmission timing, i.e., a maximum delay time permitted for the transmission. In the case of transmitting AV data using the IEEE 1394 interface as well, such transmission timing is determined by a range of the permitting time period in which each packet can be transmitted.
In general, in a packet output device, one packet per predetermined unit time which is referred to as a cycle is output to a transmitting path in an isochronous transfer mode based on the IEEE 1394 standard. For example, when a data rate is 28.8 Mbps, 250 data packets and 16 to 17 vacant packets are output for 1/30 second. Each data packet contains 480 bytes of data, and each vacant packet contains no data. The generated packets (data packets and vacant packets) are output from the packet output device.
A conventional packet output device 300 and operations thereof will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing a basic structure of the conventional packet output device 300. The packet output device 300 includes a packet generator 31, a packet transmitting circuit 32 and a clock signal generator 33.
The clock signal generator 33 outputs, for example, a clock signal having a predetermined cycle, which defines clock time for the system of the packet output device 300. The packet generator 31 generates, for example, one data packet or vacant packet per 125 .mu.s (8 kHz) based on the clock time which is defined by the clock signal output from the clock signal generator 33. The packet generator 31 outputs the generated packets to the packet transmitting circuit 32. The packet transmitting circuit 32 receives the packets and then outputs the packets to the transmitting path 34 in accordance with a predetermined transmission cycle C.
FIG. 2 is a timing chart showing an exemplary packet arrangement on the transmitting path 34. As shown in FIG. 2, a time period of each transmission cycle C is 10 t, where t is a predetermined unit of time (e.g., one cycle of a clock signal). In FIG. 2, each cycle C is shown as cycle C.sub.j (j=1, 2, 3, . . . .), and each cycle C.sub.j starts from a time (10.times.j)t. The transmitting path 34 is typically shared with another device such as a terminal, and it is assumed that the transmitting path 34 is busy from cycles C.sub.3 to C.sub.5 because of the transmission of data from the other device, as shown in FIG. 2.
The packet generator 31 generates one data packet P.sub.i (i=1, 2, 3, . . . ) every time period of 16 t, i.e., time width 16 t. Each generated packet P.sub.i can be transmitted within a time width 13 t to the transmitting path 34 via the packet transmitting circuit 32. For example, the first data packet P.sub.1 is required to be output from the packet transmitting circuit 32 to the transmitting path 34 during a time period from the time 16 t to the time 29 t. Accordingly, the data packet P.sub.1 is output in the cycle C.sub.2 which is available in this time period. Accordingly the output of the data packet P.sub.1 starts at time 20 t.
Similarly, the second data packet P.sub.2 (indicated by a broken line in FIG. 2) is required to be output to the transmitting path 34 during a time period from time 23 t to time 45 t. At this time , a cycle C.sub.4 starts at time 40 t, and therefore the data packet P.sub.2 is output in cycle C.sub.4. However, the transmitting path 34 is busy for transmitting data from the other device during cycle C.sub.4. Thus, the packet P.sub.2 cannot be transferred and thus is abandoned. Since there is no data packet to be transmitted in the previous cycle C.sub.3, a vacant packet V.sub.2 is generated in the packet generator 31 and it output to the transmitting path 34.
The third data packet P.sub.3 is to be output to the transmitting path 34 during a time period from time 48 t to time 61 t. Accordingly, the data packet P.sub.3 can be output in cycles C.sub.5 and C.sub.6 which start at time 50 t and 60 t, respectively. However, as shown in FIG. 2, since the transmitting path 34 is busy during cycle C.sub.5, the data packet P.sub.3 is output in the available cycle C.sub.6.
The fourth data packet P.sub.4 is to be output to the transmitting path 34 during a time period from time 64 t to time 77 t. During this time, an available cycle C.sub.7 starts at time 70 t, and therefore the data packet P.sub.4 is output in cycle C.sub.7. In a cycle C.sub.8, since there is no data packet to be transmitted, a vacant packet V.sub.3 is generated and output to the transmitting path 34.
The fifth data packet P.sub.5 is to be output to the transmitting path 34 during a time period from time 80 t to time 93 t. Accordingly, the data packet P.sub.5 can be output in cycles C.sub.8 and C.sub.9 which start at times 80 t and 90 t, respectively. Since cycle C.sub.8 is occupied by the vacant packet V.sub.3, the data packet P.sub.5 is output in cycle C.sub.9.
In the conventional packet device 300, as described above, the packet generator 31 generates the data packets P.sub.i (i=1, 2, 3, . . . . ), or vacant packets V.sub.k (k=1, 2, 3,, . . . . ) in the case there is no data to be transmitted, for output to the packet transmitting circuit 32 at a time (10.times.j)t at which each cycle C.sub.j starts. Accordingly, the packet generator 31 is required to generate and transmit the packets in accordance with the transmission cycle C.sub.j. The packet generator must generate and transmit the packets to the transmitting path 34, based on the clock time defined by the clock signal generated from the clock signal generator 33. For this reason, the packet generator 31 is required to constantly monitor the clock time and perform predetermined operations for each transmission cycle C.sub.j, i.e., the packet generator 31 should perform a timing control on the order of .mu.sec. This increases the load on the packet generator 31. For example, when the packet generator 31 is implemented using a microcomputer, it is necessary for the microcomputer to constantly monitor the clock time, thus reducing the time available for executing other tasks for operation processes.